Search - fir filter in vhdl

[Other resource] FPGA_FIR

Description: VHDL语言编写的FIR滤波器源码对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding
Platform: | Size: 152436 | Author: 冯申 | Hits:

[VHDL-FPGA-Verilog] fir

Description: FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
Platform: | Size: 173056 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] DIGTAL_FIR

Description: 环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform: | Size: 774144 | Author: 梁大法 | Hits:

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[Other] IIR

Description: 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
Platform: | Size: 472064 | Author: lzndcb | Hits:

[VHDL-FPGA-Verilog] filtru_fi

Description: This is a filter fir implemeted in vhdl, i hope it will work :)
Platform: | Size: 1024 | Author: om | Hits:

[VHDL-FPGA-Verilog] FIR_TEST

Description: 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块，并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we design such core modules as CIC filter, HB filter and FIR filter of the digital down converter.
Platform: | Size: 182272 | Author: 邓建良 | Hits:

[VHDL-FPGA-Verilog] LMS_filter

Description: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Platform: | Size: 350208 | Author: rayax | Hits:

[Other] filter

Description: FIR数字滤波器的实现，采用Kaiser窗实现高精度的地痛滤波器。-The realization of FIR digital filter using Kaiser window filter to achieve high accuracy in pain.
Platform: | Size: 4096 | Author: Jin Wei | Hits:

[VHDL-FPGA-Verilog] lowpassfir

Description: Low pass fir filter for ecg signal in VHDL
Platform: | Size: 1024 | Author: rohan | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 实现滤波器的功能，有限冲激响应（FIR）数字滤波器和无限冲激响应（IIR）数字滤波器广泛应用于数字信号处理系统中。IIR数字滤波器方便简单，但它相位的非线性，要求采用全通网络进行相位校正，且稳定性难以保障。FIR滤波器具有很好的线性相位特性，使得它越来越受到广泛的重视。-Realize the filter function, finite impulse response (FIR) digital filters and infinite impulse response (IIR) digital filters are widely used in digital signal processing systems. IIR digital filter to facilitate simple, but it is non-linear phase to adopt the all-pass network phase correction, and the stability can not be guaranteed. FIR filter has a good linear phase characteristics, making it more and more widely appreciated.
Platform: | Size: 945152 | Author: 陈辉 | Hits:

[VHDL-FPGA-Verilog] CSDmultiplier

Description: Code for CSD Multiplier
Platform: | Size: 1024 | Author: yuvi | Hits:

[VHDL-FPGA-Verilog] fir

Description: this file contain a description in vhdl of a fir it contain three part well described to similate the behavior of the this type of filter
Platform: | Size: 11264 | Author: seif | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[OS program] FIR

Description: an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
Platform: | Size: 3072 | Author: mohandes | Hits:

[Technology Management] FIR_poroje

Description: this project is about FIR FIlter By VHdl codes in the ISE.
Platform: | Size: 2798592 | Author: Atefeh | Hits:

[VHDL-FPGA-Verilog] fpga-fir

Description: 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog language
Platform: | Size: 1404928 | Author: 韩闯 | Hits:

[Other] E4_6_FirIpCore

Description: 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)
Platform: | Size: 1198080 | Author: cc12 | Hits:

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[Other resource] FPGA_FIR

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] DIGTAL_FIR

[VHDL-FPGA-Verilog] DA_FIR

[VHDL-FPGA-Verilog] halfband

[Other] IIR

[VHDL-FPGA-Verilog] filtru_fi

[VHDL-FPGA-Verilog] FIR_TEST

[VHDL-FPGA-Verilog] LMS_filter

[Other] filter

[VHDL-FPGA-Verilog] lowpassfir

[VHDL-FPGA-Verilog] fir_filter

[VHDL-FPGA-Verilog] CSDmultiplier

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

[VHDL-FPGA-Verilog] FIR-LOOP-

[OS program] FIR

[Technology Management] FIR_poroje

[VHDL-FPGA-Verilog] fpga-fir

[Other] E4_6_FirIpCore

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